Sometimes we need to set up a virtual environment or platform that enables testing of an application's functioning similar to that in a real world scenario, to ensure its accuracy and correctness. Such an activity of simulating the design under test and the unit under test, is done with the help of test bench.
A test bench can be defined as a set-up which enables testing of an application by replicating the real world use of the same. In software testing a file of code run on the machine to check the hardware design.
With an uprising demand for high-end digital systems, the need for verification and validation of system's functioning is really important. Hardware's Description Language (HDL) code is used to produce a documented, repeatable set of test reports that can be used across different simulators. Two very common HDL's are Verilog and VHDL.
Often our test strategy focuses on finding defects in the system. This approach restricts delving deeper into the application, therefore, test bench offers a solution by allowing testers to carry out more rigorous testing to understand the functioning even better. A test bench can be created using either of the following ways :
VHDL :This language has its roots in Ada programming language. VHDL stands for VHSIC Hardware Description Language used primarily in electronic design automation. This is a strongly typed language.
Verilog :This is again an HDL that is used in digital electronic systems, analog circuits and mixed signal circuits. Verilog is a loosely typed language but has efficient notation.
Device Under Test (DUT) :A device under test can be simply thought of as a replica of the actual design or something that is a behavioural representation of a design.
Typically in the process of test bench, a code file is executed written in a simulation specific language. Now let us take Verilog as an example in the context of test bench. When we begin working on a verilog file, the code is written in such a way so as to match up with the hardware specification.
module basic_and #(parameter WIDTH = 1)(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] out
assign out = a & b;
The above code is just to develop a better understanding of how a verilog code module looks like. This code simply takes few variables as inputs, ANDs them and produces an output. Now if one wishes to make sure that the module delivers the expected output, then we must write a test bench associated with the module to validate its functioning.
reg [3:0] a, b;
wire [3:0] out;
basic_and #(.WIDTH(4)) DUT (
a = 4'b0000;
b = 4'b0000;
a = 4'b1111;
b = 4'b0101;
a = 4'b1100;
b = 4'b1111;
a = 4'b1100;
b = 4'b0011;
a = 4'b1100;
b = 4'b1010;
Typically a test bench begins with the name of the module and a module does not have any inputs or outputs , it is completely an intact code. A clock pulse initiates an action and the module's execution follows the clock signals. This is precisely how a test bench is conducted.