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Test Bench


Introduction :

Sometimes we need to set up a virtual environment or platform that enables testing of an application's functioning similar to that in a real world scenario, to ensure its accuracy and correctness. Such an activity of simulating the design under test and the unit under test, is done with the help of test bench.

A test bench can be defined as a set-up which enables testing of an application by replicating the real world use of the same. In software testing a file of code run on the machine to check the hardware design.

With an uprising demand for high-end digital systems, the need for verification and validation of system's functioning is really important. Hardware's Description Language (HDL) code is used to produce a documented, repeatable set of test reports that can be used across different simulators. Two very common HDL's are Verilog and VHDL.

Often our test strategy focuses on finding defects in the system. This approach restricts delving deeper into the application, therefore, test bench offers a solution by allowing testers to carry out more rigorous testing to understand the functioning even better. A test bench can be created using either of the following ways :

  • Text Editor- Recommended for verifying quite complex designs, that allows using the available features in HDL. Offers a lot of flexibility in managing code and helps to produce precise and accurate results.
  • Xilinx Test bench Waveform Editor- Ideal for less complex simulation tasks, recommended for use by comparatively new users.

VHDL :This language has its roots in Ada programming language. VHDL stands for VHSIC Hardware Description Language used primarily in electronic design automation. This is a strongly typed language.

Verilog :This is again an HDL that is used in digital electronic systems, analog circuits and mixed signal circuits. Verilog is a loosely typed language but has efficient notation.

Device Under Test (DUT) :A device under test can be simply thought of as a replica of the actual design or something that is a behavioural representation of a design.

Components of Test Bench :

  • Input -This includes the requirements that are needed to perform work. Basically this is the entrance criteria for the test bench.
  • Output -It consists of the exit criteria or we can say the deliverables achieved at the end of the test bench.
  • Procedures to -The processes that will transfer the inputs into outputs.
  • Procedures to check -These are the processes that determine whether the output meet the required standard.

Types of Test Bench :

  • Stimulus Only -Contains only the driver containing the stimulus driver and the Design under test but does not contain any result verification.
  • Full Test bench -This test bench contains the stimulus driver, the correct results and results for comparison.
  • Simulator specific - The name suggests that the test bench is written in a simulator specific format.
  • Hybrid test bench -This is a blend of techniques from more than one test bench style.
  • Fast test bench -It is to optimize the speed of a test bench. This is written in a way so as to provide the best speed from a simulation.

Summary :

Typically in the process of test bench, a code file is executed written in a simulation specific language. Now let us take Verilog as an example in the context of test bench. When we begin working on a verilog file, the code is written in such a way so as to match up with the hardware specification.

module basic_and #(parameter WIDTH = 1)(

input [WIDTH-1:0] a,

input [WIDTH-1:0] b,

output [WIDTH-1:0] out

);

assign out = a & b;

endmodule

The above code is just to develop a better understanding of how a verilog code module looks like. This code simply takes few variables as inputs, ANDs them and produces an output. Now if one wishes to make sure that the module delivers the expected output, then we must write a test bench associated with the module to validate its functioning.

module basic_and_tb();

reg [3:0] a, b;

wire [3:0] out;

basic_and #(.WIDTH(4)) DUT (

.a(a),

.b(b),

.out(out)

);

initial begin

a = 4'b0000;

b = 4'b0000;

#20

a = 4'b1111;

b = 4'b0101;

#20

a = 4'b1100;

b = 4'b1111;

#20

a = 4'b1100;

b = 4'b0011;

#20

a = 4'b1100;

b = 4'b1010;

#20

$finish;

end

endmodule

Typically a test bench begins with the name of the module and a module does not have any inputs or outputs , it is completely an intact code. A clock pulse initiates an action and the module's execution follows the clock signals. This is precisely how a test bench is conducted.